Integrated circuits are fabricated by growing, depositing, diffusing, and etching thin layers of conductors, insulators, and semiconductors onto a substrate having a semiconductor layer, such as silicon. To keep the fabrication processes operating properly, or to diagnose and correct the process when a defect does occur, process engineers must be able to quickly examine the various processed layers.
A primary tool used for examining, analyzing, and repairing processing layers is a focused ion beam (FIB) system. FIB systems improve manufacturing yields by identifying and analyzing defects on in-process wafers, allowing the source of defects to be located and corrected. For example, layers can be sputter-etched by a FIB system to expose underlying layers for observation and testing, or cross sections can be cut to expose the edges of multiple layers to observe layer thickness, uniformity, and inclusions.
FIB systems are also useful in the design or prototyping stages of integrated circuit designs. When a prototype integrated circuit is fabricated and tested, it is often found that changes to the circuit design are necessary. A FIB system can modify an integrated circuit, allowing changes to be rapidly implemented and tested without having to modify the photolithography masks and re-run the manufacturing process to create a new prototype. Such changes are called “device edits.” For example, a FIB system can be used to sever electrical connections by etching through conductors or to create new connections by the selective deposition of conductive materials. The design changes made using FIB device edits can be verified by subsequent electrical testing and incorporated into a final mask design to be used for mass production of the integrated circuit.
During the device edits, it may be necessary to create electrical connections between buried connectors. This can be done by FIB milling holes, or “vias”, through the insulating layers above a conductor to expose the underlying conductor. When the underlying conductors are deeply buried, however, the material sputtered at the bottom of the hole during milling tends to redeposit on the side walls of the hole. Thus, it becomes difficult to mill a hole having a high aspect ratio, that is, a hole much deeper than it is wide or long. Accordingly, as the number of metal conductive layers in a device increases, the more difficult the FIB milling process becomes. Unfortunately, with the dense packing of modem integrated circuits, a wide hole may damage or expose circuitry in other layers, including the conductive metal layers of the interconnect structure. Such damage or exposure can result in shorts or opens in these metal layers. However, damage is not limited to the conductive layers of the interconnect structure. The dielectric materials of the interconnect structure can be damaged as well during the FIB milling process. Although any dielectric material is generally susceptible to FIB damage, in low density dielectric materials, such as low-k dielectrics, the amount of damage can increase significantly and can undesirably raise the dielectric constant.